Flash EEprom system

ABSTRACT

A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

BACKGROUND OF THE INVENTION

[0001] This invention relates generally to semiconductor electricallyerasable programmable read only memories (EEprom), and specifically to asystem of integrated circuit Flash EEprom chips.

[0002] Computer systems typically use magnetic disk drives for massstorage of data. However, disk drives are disadvantageous in that theyare bulky and in their requirement for high precision moving mechanicalparts. Consequently they are not rugged and are prone to reliabilityproblems, as well as consuming significant amounts of power. Solid statememory devices such as DRAM's and SRAM's do not suffer from thesedisadvantages. However, they are much more expensive, and requireconstant power to maintain their memory (volatile). Consequently, theyare typically used as temporary storage.

[0003] EEprom's and Flash EEprom's are also solid state memory devices.Moreover, they are nonvolatile, and retain their memory even after poweris shut down. However, conventional Flash EEprom's have a limitedlifetime in terms of the number of write (or program)/erase cycles theycan endure. Typically the devices are rendered unreliable after 10² to10³ write/erase cycles. Traditionally, they are typically used inapplications where semi-permanent storage of data or program is requiredbut with a limited need for reprogramming.

[0004] Accordingly, it is an object of the present invention to providea Flash EEprom memory system with enhanced performance and which remainsreliable after enduring a large number of write/erase cycles.

[0005] It is another object of the present invention to provide animproved Flash EEprom system which can serve as non-volatile memory in acomputer system.

[0006] It is another object of the present invention to provide animproved Flash EEprom system that can replace magnetic disk storagedevices in computer systems.

[0007] It is another object of the present invention to provide a FlashEEprom system with improved erase operation.

[0008] It is another object of the present invention to provide a FlashEEprom system with improved error correction.

[0009] It is yet another object of the present invention to provide aFlash EEprom with improved write operation that minimizes stress to theFlash EEprom device.

[0010] It is still another object of the present invention to provide aFlash EEprom system with enhanced write operation.

SUMMARY OF THE INVENTION

[0011] These and additional objects are accomplished by improvements inthe architecture of a system of EEprom chips, and the circuits andtechniques therein.

[0012] According to one aspect of the present invention, an array ofFlash EEprom cells on a chip is organized into sectors such that allcells within each sector are erasable at once. A Flash EEprom memorysystem comprises one or more Flash EEprom chips under the control of acontroller. The invention allows any combination of sectors among thechips to be selected and then erased simultaneously. This is faster andmore efficient than prior art schemes where all the sectors must beerased every time or only one sector at a time can be erased. Theinvention further allows any combination of sectors selected for eraseto be deselected and prevented from further erasing during the eraseoperation. This feature is important for stopping those sectors that arefirst to be erased correctly to the “erased” state from over erasing,thereby preventing unnecessary stress to the Flash EEprom device. Theinvention also allows a global de-select of all sectors in the system sothat no sectors are selected for erase. This global reset can quicklyput the system back to its initial state ready for selecting the nextcombination of sectors for erase. Another feature of the invention isthat the selection is independent of the chip select signal whichenables a particular chip for read or write operation. Therefore it ispossible to perform an erase operation on some of the Flash EEprom chipswhile read and write operations may be performed on other chips notinvolved in the erase operation.

[0013] According to another aspect of the invention, improved errorcorrection circuits and techniques are used to correct for errorsarising from defective Flash EEprom memory cells. One feature of theinvention allows defect mapping at cell level in which a defective cellis replaced by a substitute cell from the same sector. The defectpointer which connects the address of the defective cell to that of thesubstitute cell is stored in a defect map. Every time the defective cellis accessed, its bad data is replaced by the good data from thesubstitute cell.

[0014] Another feature of the invention allows defect mapping at thesector level. When the number of defective cells in a sector exceeds apredetermined number, the sector containing the defective cells isreplaced by a substitute sector.

[0015] An important feature of the invention allows defective cells ordefective sectors to be remapped as soon as they are detected therebyenabling error correction codes to adequately rectify the relatively fewerrors that may crop up in the system.

[0016] According to yet another aspect of the present invention, a writecache is used to minimize the number of writes to the Flash EEprommemory. In this way the Flash EEprom memory will be subject to fewerstress inducing write/erase cycles, thereby retarding its aging. Themost active data files are written to the cache memory instead of theFlash EEprom memory. Only when the activity levels have reduced to apredetermined level are the data files written from the cache memory tothe Flash EEprom memory. Another advantage of the invention is theincrease in write throughput by virtue of the faster cache memory.

[0017] According to yet another aspect of the present invention, one ormore printed circuit cards are provided which contain controller andEEprom circuit chips for use in a computer system memory for long term,non-volatile storage, in place of a hard disk system, and whichincorporate various of the other aspects of this invention alone and incombination.

[0018] Additional objects, features, and advantages of the presentinvention will be understood from the following description of itspreferred embodiments, which description should be taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1A is a general micrprocessor system including, the FlashEEprom memory system of the present invention;

[0020]FIG. 1B is schematic block diagram illustrating a system includinga number of Flash EEprom memory chips and a controller chip;

[0021]FIG. 2 is a schematic illustration of a system of Flash EEpromchips, among which memory sectors are selected to be erased;

[0022]FIG. 3A is a block circuit diagram in the controller forimplementing selective multiple sector erase according to the preferredembodiment;

[0023]FIG. 3B shows details of a typical register used to select asector for erase as shown in FIG. 2A;

[0024]FIG. 4 is a flow diagram illustrating the erase sequence ofselective multiple sector erase;

[0025]FIG. 5 is a schematic illustration showing the partitioning of aFlash EEprom sector into a data area and a spare redundant area;

[0026]FIG. 6 is a circuit block diagram illustrating the data pathcontrol during read operation using the defect mapping scheme of thepreferred embodiment;

[0027]FIG. 7 is a circuit block diagram illustrating the data pathcontrol during the write operation using the defect mapping scheme ofthe preferred embodiment;

[0028]FIG. 8 is a block diagram illustrating the write cache circuitinside the controller.

DESCRIPTION OF THE PREFERRED EMBODIMENTS EEprom SYSTEM

[0029] A computer system in which the various aspects of the presentinvention are incorporated is illustrated generally in FIG. 1A. Atypical computer system architecture includes a microprocessor 21connected to a system bus 23, along with random access, main systemmemory 25, and at least one or more input-output devices 27, such as akeyboard, monitor, modem, and the like. Another main computer systemcomponent that is connected to a typical computer system bus 23 is alarge amount of long-term, non-volatile memory 29. Typically, such amemory is a disk drive with a capacity of tens of megabytes of datastorage. This data is retrieved into the system volatile memory 25 foruse in current processing, and can be easily supplemented, changed oraltered.

[0030] One aspect of the present invention is the substitution of aspecific type of semiconductor memory system for the disk drive butwithout having to sacrifice non-volatility, ease of erasing andrewriting data into the memory, speed of access, low cost andreliability. This is accomplished by employing an array of electricallyerasable programmable read only memories (EEprom's) integrated circuitchips. This type of memory has additional advantages of requiring lesspower to operate, and of being lighter in weight than a hard disk drivemagnetic media memory, thereby being especially suited for batteryoperated portable computers.

[0031] The bulk storage memory 29 is constructed of a memory controller31, connected to the computer system bus 23, and an array 33 of EEpromintegrated circuit chips. Data and instructions are communicated fromthe controller 31 to the EEprom array 33 primarily over a serial dataline 35. Similarly, data and status signals are communicated from theEEprom 33 to the controller 31 over serial data lines 37. Other controland status circuits between the controller 31 and the EEprom array 33are not shown in FIG. 1A.

[0032] Referring to FIG 1B, the controller 31 is preferably formedprimarily on a single integrated circuit chip. It is connected to thesystem address and data bus 39, part of the system bus 33, as well asbeing connected to system control lines 41, which include interrupt,read, write and other usual computer system control lines.

[0033] The EEprom array 33 includes a number of EEprom integratedcircuit chips 43, 45, 47, etc. Each includes a respective chip selectand enable line 49, 51 and 53 from interface circuits 40. The interfacecircuits 40 also act to interface between the serial data lines 35, 37and a circuit 55. Memory location addresses and data being written intoor read from the EEprom chips 43, 45, 47, etc. are communicated from abus 55, through logic and register circuits 57 and thence by another bus59 to each of the memory chips 43, 45, 47 etc.

[0034] The bulk storage memory 29 of FIGS 1A and 1B can be implementedon a single printed circuit card for moderate memory sizes. The variouslines of the system buses 39 and 41 of FIG. 1B are terminated inconnecting pins of such a card for connection with the rest of thecomputer system through a connector. Also connected to the card and itscomponents are various standard power supply voltages (not shown).

[0035] For large amounts of memory, that which is conveniently providedby a single array 33 may not be enough. In such a case, additionalEEprom arrays can be connected to the serial data lines 35 and 37 of thecontroller chip 31, as indicated in FIG 1B. This is preferably all doneon a single printed circuit card but if space is not sufficient to dothis, then one or more EEprom arrays may be implemented on a ,secondprinted circuit card that is physically mounted onto the first andconnected to a common controller chip 31.

[0036] Erase of Memory Structures

[0037] In system designs that store data in files or blocks the datawill need to be periodically updated with revised or new information. Itmay also be desirable to overwrite some no longer needed information, inorder to accommodate additional information. In a Flash EEprom memory,the memory cells must first be erased before information is placed inthem. That is, a write (or program) operation is always preceded by anerase operation.

[0038] In conventional Flash erase memory devices, the erase operationis done in one of several ways. For example, in some devices such as theIntel corporation's model 27F-256 CMOS Flash EEprom, the entire chip iserased at one time. If not all the information in the chip is to beerased, the information must first be temporarily saved, and is usuallywritten into another memory (typically RAM). The information is thenrestored into the nonvolatile Flash erase memory by programming backinto the device. This is very slow and requires extra memory as holdingspace.

[0039] In other devices such as Seeq Technology Incorporated's model48512 Flash EEprom chip, the memory is divided into blocks (or sectors)that are each separately erasable, but only one at a time. By selectingthe desired sector and going through the erase sequence the designatedarea is erased. While, the need for temporary memory is reduced, erasein various areas of the memory still requires a time consumingsequential approach.

[0040] In the present invention, the Flash EEprom memory is divided intosectors where all cells within each sector are erasable together. Eachsector can be addressed separately and selected for erase. One importantfeature is the ability to select any combination of sectors for erasetogether. This will allow for a much faster system erase than by doingeach one independently as in prior art.

[0041]FIG. 2 illustrates schematically selected multiple sectors forerase. A Flash EEprom system includes one or more Flash EEprom chipssuch as 201, 203, 205. They are in communication with a controller 31through lines 209. Typically, the controller 31 is itself incommunication with a microprocessor system (not shown). The memory ineach Flash EEprom chip is partitioned into sectors where all memorycells within a sector are erasable together. For example, each sectormay have 512 byte (i.e. 512×8 cells) available to the user, and a chipmay have 1024 sectors. Each sector is individually addressable, and maybe selected, such as sectors 211, 213, 215, 217 in a multiple sectorerase. As illustrated in FIG. 2, the selected sectors may be confined toone EEprom chip or be distributed among several chips in a system. Thesectors that were selected will all be erased together. This capabilitywill allow the memory and system of the present invention to operatemuch faster than the prior art architectures.

[0042]FIG. 3A illustrates a block diagram circuit 220 on a Flash EEpromchip (such as the chip 201 of FIG. 2) with which one or more sectorssuch as 211, 213 are selected (or deselected) for erase. Essentially,each sector such as 211, 213 is selected or tagged by setting the stateof an erase enable register such as 221, 223 associated with therespective sectors. The selection and subsequent erase operations areperformed under the control of the controller 31 (see FIG. 2). Thecircuit 220 is in communication with the controller 31 through lines209. Command information from the controller is captured in the circuit220 by a command register 225 through a serial interface 227. It is thendecoded by a command decoder 229 which outputs various control signals.Similarly, address information is captured by an address register 231and is decoded by an address decoder 233.

[0043] For example, in order to select the sector 211 for erase, thecontroller sends the address of the sector 211 to the circuit 220. Theaddress is decoded in line 235 and is used in combination with a seterase enable signal in bus 237 to set an output 239 of the register 221to HIGH. This enables the sector 211 in a subsequent erase operation.Similarly, if the sector 213 is also desired to be erased, itsassociated register 223 may be set HIGH.

[0044]FIG. 3B shows the structure of the register such as 221, 223 inmore detail. The erase enable register 221 is a SET/RESET latch. Its setinput 241 is obtained from the set erase enable signal in bus 237 gatedby the address decode in line 235. Similarly, the reset input 243 isobtained from the clear erase enable signal in bus 237 gated by theaddress decode in line 235. In this way, when the set erase enablesignal or the clear erase enable signal is issued to all the sectors,the signal is effective only on the sector that is being addressed.

[0045] After all sectors intended for erase have been selected, thecontroller then issues to the circuit 220, as well as all other chips inthe system a global erase command in line 251 along with the highvoltage for erasing in line 209. The device will then erase all thesectors that have been selected (i.e. the sectors 211 and 213) at onetime. In addition to erasing the desired sectors within a chip, thearchitecture of the present system permits selection of sectors acrossvarious chips for simultaneous erase.

[0046] FIGS. 4(1)-4(11) illustrate the algorithm used in conjunctionwith the circuit 220 of FIG. 3A. In FIG. 4(1), the controller will shiftthe address into the circuit 220 which is decoded in the line to theerase enable register associated with the sector that is to be erased.In FIG. 4(2), the controller shifts in a command that is decoded to aset erase enable command which is used to latch the address decodesignal onto the erase enable register for the addressed sector. Thistags the sector for subsequent erase. In FIG. 4(3), if more sectors areto be tagged, the operations described relative to FIGS. 4(1)-4(2) arerepeated until all sectors intended for erase have been tagged. Afterall sectors intended for erase have been tagged, the controllerinitiates an erase cycle as illustrated in FIG. 4(4).

[0047] Optimized erase implementations have been disclosed in twocopending U.S. patent applications. They are copending U.S. patentapplications, Ser. No. 204,175, filed Jun. 8, 1988, by Dr. EliyahouHarari and one entitled “Multi-State EEprom Read and Write Circuits andTechniques,” filed on the same day as the present application, by SanjayMehrotra and Dr. Eliyahou Harari. The disclosures of the twoapplications are hereby incorporate by reference. The Flash EEprom cellsare erased by applying a pulse of erasing voltage followed by a read toverify if the cells are erased to the “erased” state. If not, furtherpulsing and verifying are repeated until the cells are verified to beerased. By erasing in this controlled manner, the cells are not subjectto over-erasure which tends to age the EEprom device prematurely as wellas make the cells harder to program.

[0048] As the group of selected sectors is going through the erasecycle, some sectors will reach the “erase” state earlier than others.Another important feature of the present invention is the ability toremove those sectors that have been verified to be erased from the groupof selected sectors, thereby preventing them from over-erasing.

[0049] Returning to FIG. 4(4), after all sectors intended for erase havebeen tagged, the controller initiates an erase cycle to erase the groupof tagged sectors. In FIG. 4(5), the controller shifts in a globalcommand called Enable Erase into each Flash EEprom chip that is toperform an erase. This is followed in FIG. 4(5) by the controllerraising of the erase voltage line (Ve) to a specified value for aspecified duration. The controller will lower this voltage at the end ofthe erase duration time. In FIG. 4(6), the controller will then do aread verify sequence on the sectors selected for erase. In FIG. 4(7), ifnone of the sectors are verified, the sequences illustrated in FIGS.4(5)-4(7) are repeated. In FIGS. 4(8) and 3(9), if one or more sectorsare verified to be erased, they are taken out of the sequence. Referringalso to FIG. 3A, this is achieved by having the controller address eachof the verified sectors and clear the associated erase enable registersback to a LOW with a clear enable command in bus 237. The sequencesillustrated in FIGS. 4(5)-4(10) are repeated until all the sectors inthe group are verified to be erased in FIG. 4(11). At the completion ofthe erase cycle, the controller will shift in a No Operation (NOP)command and the global Enable Erase command will be withdrawn as aprotection against a false erasure.

[0050] The ability to select which sectors to erase and which ones notto, as well as which ones to stop erasing is advantageous. It will allowsectors that have erased before the slower erased sectors to be removedfrom the erase sequence so no further stress on the device will occur.This will increase the reliability of the system. Additional advantageis that if a sector is bad or is not used for some reason, that sectorcan be skipped over with no erase occurring within that sector. Forexample, if a sector is defective and have shorts in it, it may consumemuch power. A significant system advantage is gained by the presentinvention which allows it to be skipped on erase cycles so that it maygreatly reduce the power required to erase the chip.

[0051] Another consideration in having the ability to pick the sectorsto be erased within a device is the power savings to the system. Theflexibility in erase configuration of the present invention enables theadaptation of the erase needs to the power capability of the system.This can be done by configuring the systems to be erased differently bysoftware on a fixed basis between different systems. It also will allowthe controller to adaptively change the amount of erasing being done bymonitoring the voltage level in a system, such as a laptop computer.

[0052] An additional performance capability of the system in the presentinvention is the ability to issue a reset command to a Flash EEprom chipwhich will clear all erase enable latches and will prevent any furthererase cycles from occurring. This is illustrated in FIGS. 2A and 2B bythe reset signal in the line 261. By doing this in a global way to allthe chips, less time will be taken to reset all the erase enableregisters.

[0053] An additional performance capability is to have the ability to doerase operations without regard to chip select. Once an erase is startedin some of the memory chips, the controller in the system can accessother memory chips and do read and write operations on them. Inaddition, the device(s) doing the erase can be selected and have anaddress loaded for the next command following the erase.

[0054] Defect Mapping

[0055] Physical defects in memory devices give rise to hard errors. Databecomes corrupted whenever it is stored in the defective cells. Inconventional memory devices such as RAM's and Disks, any physicaldefects arising from the manufacturing process are corrected at thefactory. In RAM's, spare redundant memory cells on chip may be patchedon, in place of the defective cells. In the traditional disk drive, themedium is imperfect and susceptible to defects. To overcome this problemmanufacturers have devised various methods of operating with thesedefects present, the most usual being defect mapping of sectors. In anormal disk system the media is divided into cylinders and sectors. Thesector being the basic unit in which data is stored. When a system ispartitioned into the various sectors the sectors containing the defectsare identified and are marked as bad and not to be used by the system.This is done in several ways. A defect map table is stored on aparticular portion of the disk to be used by the interfacing controller.In addition, the bad sectors are marked as bad by special ID and flagmarkers. When the defect is addressed, the data that would normally bestored there is placed in an alternative location. The requirement foralternative sectors makes the system assign spare sectors at somespecific interval or location. This reduces the amount of memorycapacity and is a performance issue in how the alternative sectors arelocated.

[0056] One important application of the present invention is to replacea conventional disk storage device with a system incorporating an arrayof Flash EEprom memory chips. The EEprom system is preferably set up toemulate a conventional disk, and may be regarded as a “solid-statedisk”.

[0057] In a “disk” system made from such solid-state memory devices, lowcost considerations necessitate efficient handling of defects. Anotherimportant feature of the invention enables the error correction schemeto conserve as much memory as possible. Essentially, it calls for thedefective cells to be remapped cell by cell rather than by throwing awaythe whole sector (512 bytes typically) whenever a defect occurs in it.This scheme is especially suited to the Flash EEprom medium since themajority of errors will be bit errors rather than a long stream ofadjacent defects as is typical in traditional disk medium.

[0058] In both cases of the prior art RAM and magnetic disk, once thedevice is shipped from the factory, there is little or no provision forreplacing hard errors resulting from physical defects that appear laterduring normal operation. Error corrections then mainly rely on schemesusing error correction codes (ECC).

[0059] The nature of the Flash EEprom device predicates a higher rate ofcell failure especially with increasing program/erase cycling. The harderrors that accumulate with use would eventually overwhelm the ECC andrender the device unusable. One important feature of the presentinvention is the ability for the system to correct for hard errorswhenever they occur. Defective cells are detected by their failure toprogram or erase correctly. Also during read operation, defective cellsare detected and located by the ECC. As soon as a defective cell isidentified, the controller will apply defect mapping to replace thedefective cell with a space cell located usually within the same sector.This dynamic correction of hard errors, in addition to conventionalerror correction schemes, significantly prolongs the life of the device.

[0060] Another feature of the present invention is an adaptive approachto error correction. Error correction code (ECC) is employed at alltimes to correct for soft errors as well as any hard errors that mayarise. As soon as a hard error is detected, defect mapping is used toreplace the defective cell with a spare cell in the same sector block.only when the number of defective cells in a sector exceeds the defectmapping's capacity for that specific sector will the whole sector bereplaced as in a conventional disk system. This scheme minimized wastagewithout compromising reliability.

[0061]FIG. 5 illustrates the memory architecture for the cell remappingscheme. As described before, the Flash EEprom memory is organized intosectors where the cells in each sector are erasable together. The memoryarchitecture has a typical sector 401 organized into a data portion 403and a spare (or shadow) portion 405. The data portion 403 is memoryspace available to the user. The,spare portion 405 is further organizedinto an alternative defects data area 407, a defect map area 409, aheader area 411 and an ECC and others area 413. These areas containinformation that could be used by the controller to handle the defectsand other overhead information such as headers and ECC.

[0062] Whenever a defective cell is detected in the sector, a good cellin the alternative defects data area 407 is assigned to backup the datadesignated for the defective cell. Thus even if the defective cellstores the data incorrectly, an error-free copy is stored in the backupcell. The addresses of the defective cell and the backup cell are storedas defect pointers in the defect map 409.

[0063] It is to be understood that the partitioning between the userdata portion 403 and the spare portion 405 need not be rigid. Therelative size of the various partitioned areas may be logicallyreassigned. Also the grouping of the various areas is largely for thepurpose of discussion and not necessarily physically so. For example,the alternative defects data area 407 has been schematically groupedunder the spare portion 405 to express the point that the space itoccupies is no longer available to the user.

[0064] In a read operation, the controller first reads the header, thedefect map and the alternative defects data. It then reads the actualdata. It keeps track of defective cells and the location of thesubstitute data by means of the defect map. Whenever a defective cell isencountered, the controller substitutes its bad data with the good datafrom the alternative defects.

[0065]FIG. 6 illustrates the read data path control in the preferredembodiment. A memory device 33 which may include a plurality of FlashEEprom chips is under the control of the controller 31. The controller31 is itself part of a microcomputer system under the control of amicroprocessor (not shown). To initiate the reading of a sector, themicroprocessor loads a memory address generator 503 in the controllerwith a memory address for starting the read operation. This informationis loaded through a microprocessor interface port 505. Then themicroprocessor loads a DMA controller 507 with the starting location inbuffer memory or bus address that the data read should be sent. Then themicroprocessor loads the header information (Head, Cylinder and sector)into a holding register file 509. Finally, the microprocessor loads acommand sequencer 511 with a read command before passing control to thecontroller 31.

[0066] After assuming control, the controller 31 first addresses theheader of the sector and verifies that the memory is accessed at theaddress that the user had specified. This is achieved by the followingsequence. The controller selects a memory chip (chip select) among thememory device 33 and shifts the address for the header area from theaddress generator 503 out to the selected memory chip in the memorydevice 33. The controller then switches the multiplexer 513 and shiftsalso the read command out to the memory device 33. Then the memorydevice reads the address sent it and begins sending serial data from theaddressed sector back to the controller. A receiver 515 in thecontroller receives this data and puts it in parallel format. In oneembodiment, once a byte (8 bits) is compiled, the controller comparesthe received data against the header data previously stored by themicroprocessor in the holding register file 509. If the compare iscorrect, the proper location is verified and the sequence continues.

[0067] Next the controller 31 reads the defect pointers and loads thesebad address locations into the holding register file 509. This isfollowed by the controller reading the alternative defects data thatwere written to replace the bad bits as they were written. Thealternative bits are stored in an alternative defects data file 517 thatwill be accessed as the data bits are read.

[0068] Once the Header has been determined to be a match and the defectpointers and alternative bits have been loaded, the controller begins toshift out the address of the lowest address of the desired sector to beread. The data from the sector in the memory device 33 is then shiftedinto the controller chip 31. The receiver 515 converts the data to aparallel format and transfers each byte into a temporary holding FIFO519 to be shipped out of the controller.

[0069] A pipeline architecture is employed to provide efficientthroughput as the data is gated through the controller from the receiver515 to the FIFO 519. As each data bit is received from memory thecontroller is comparing the address of the data being sent (stored inthe address generator 507) against the defect pointer map (stored in theregister file 509). If the address is determined to be a bad location,by a match at the output of the comparator 521, the bad bit from thememory received by the receiver 515 is replaced by the good bit for thatlocation. The good bit is obtained from the alternative defects datafile 517. This is done by switching the multiplexer 523 to receive thegood bit from the alternative defects data file instead of the bad bitfrom the receiver 515, as the data is sent to the FIFO 519. once thecorrected data is in the FIFO it is ready to be sent to buffer memory orsystem memory (not shown). The data is sent from the controller's FIFO519 to the system memory by the controller's DMA controller 507. Thiscontroller 507 then requests and gets access to the system bus and putsout an address and gates the data via an output interface 525 out to thesystem bus. This is done as each byte gets loaded into the FIFO 519. Asthe corrected data is loaded into the FIFO it will also be gated into anECC hardware 527 where the data file will be acted on by the ECC.

[0070] Thus in the manner described, the data read from the memorydevice 33 is gated through the controller 31 to be sent to the system.This process continues until the last bit of addressed data has beentransferred.

[0071] In spite of defect mapping of previously detected defectivecells, new hard errors might occur since the last mapping. As thedynamic defect mapping constantly “puts away” new defective cells, thelatest hard error that may arise between defect mapping would beadequately handled by the ECC. As the data is gated through thecontroller 31, the controller is gating the ECC bits into the ECChardware 527 to determine if the stored value matched the justcalculated remainder value. If it matches then the data transferred outto the system memory was good and the read operation was completed.However, if the ECC registers an error then a correction calculation onthe data sent to system memory is performed and the corrected datare-transmitted. The method for calculating the error can be done inhardware or software by conventional methods. The ECC is also able tocalculate and locate the defective cell causing the error. This may beused by the controller 31 to update the defect map associated with thesector in which the defective cell is detected. In this manner, harderrors are constantly removed from the Flash EEprom system.

[0072]FIG. 7 illustrates the write data path control in the preferredembodiment. The first portion of a write sequence is similar to a readsequence described previously. The microprocessor first loads theAddress pointers for the memory device 33 and the DMA as in-the readsequence. It also loads the header desired into the address generator503 and the command queue into the command sequencer 511. The commandqueue is loaded with a read header command first. Thereafter, control ispassed over to the controller 31. The controller then gates the addressand command to the memory device 33, as in the read sequence. The memorydevice returns header data through controller's receiver 515. Thecontroller compares the received header data to the expected value(stored in the holding register file 509). If the compare is correct,the proper location is verified and the sequence continues. Then thecontroller loads the defective address pointers from the memory device33 into the holding register file 509 and the alternative data into thealternative defects data file 517.

[0073] Next, the controller begins to fetch the write data from systemmemory (not shown). It does this by getting access to the system bus,outputs the memory or bus address and does the read cycle. It pulls thedata into a FIFO 601 through an input interface 603. The controller thenshifts the starting sector address (lowest byte address) from theaddress generator 503 to the selected memory device 33. This is followedby data from the FIFO 601. These data are routed through multiplexers605 and 513 and converted to serial format before being sent to thememory device 33. This sequence continues until all bytes for a writecycle have been loaded into the selected memory.

[0074] A pipeline architecture is employed to provide efficientthroughput as the data is gated from the FIFO 601 to the selected memory33. The data gated out of the FIFO 601 is sent to the ECC hardware 527where a remainder value will be calculated within the ECC. In the nextstage, as the data is being sent to the memory device throughmultiplexers 605 and 513, the comparator 521 is comparing its addressfrom the address generator 503 to the defect pointer address values inthe holding register file 509. When a match occurs, indicating that adefective location is about to be written, the controller saves this bitinto the alternative defect data file 517. At the same time, all badbits sent to memory will be sent as zeroes.

[0075] After the bytes for a write cycle have been loaded into theselected memory device, the controller issues a program command to thememory device and initiate a write cycle. Optimized implementations ofwrite operation for Flash EEprom device have been disclosed in twopreviously cited co-pending U.S. patent applications, Ser. No. 204,175,and one entitled “Multi-State EEprom Read and Write Circuits andTechniques.” Relevant portions of the disclosures are herebyincorporated by reference. Briefly, during the write cycle, thecontroller applies a pulse of programming (or writing) voltages. This isfollowed by a verify read to determine if all the bits have beenprogrammed properly. If the bits did not verify, the controller repeatsthe program/verify cycle until all bits are correctly programmed.

[0076] If a bit fails to verify after prolonged program/verify cycling,the controller will designate that bit as defective and update thedefect map accordingly. The updating is done dynamically, as soon as thedefective cell is detected. Similar actions are taken in the case offailure in erase verify.

[0077] After all the bits have been programmed and verified, thecontroller loads the next data bits from the FIFO 601 and addresses thenext location in the addressed sector. It then performs anotherprogram/verify sequence on the next set of bytes. The sequence continuesuntil the end of the data for that sector. Once this has occurred, thecontroller addresses the shadow memory (header area) associated with thesector (see FIG. 5) and writes the contents of the ECC registers intothis area.

[0078] In addition, the collection of bits that was flagged as defectiveand were saved in the alternative defects data file 516 is then writtenin memory at the alternative defects data locations (see FIG. 5),thereby saving the good bit values to be used on a subsequent read. Oncethese data groups are written and verified, the sector write isconsidered completed.

[0079] The present invention also has provision for defect mapping ofthe whole sector, but only after the number of defective cells in thesector has exceeded the cell defect mapping's capacity for that-specificsector. A count is kept of the number of defective cells in each sector.When the number in a sector exceeds a predetermined value, thecontroller marks that sector as defective and maps it to another sector.The defect pointer for the linked sectors may be stored in a sectordefect map. The sector defect map may be located in the originaldefective sector if its spare area is sufficiently defect-free. However,when the data area of the sector has accumulated a large number ofdefects, it is quite likely that the spare area will also be full ofdefects.

[0080] Thus, it is preferable in another embodiment to locate the sectormap in another memory maintained by the controller. The memory may belocated in the controller hardware or be part of the Flash EEprommemory. When the controller is given an address to access data, thecontroller compares this address against the sector defect map. If amatch occurs then access to, the defective sector is denied and thesubstitute address present in the defect map is entered, and thecorresponding substitute sector is accessed instead.

[0081] In yet another embodiment, the sector remapping is performed bythe microprocessor. The microprocessor looks at the incoming address andcompares it against the sector defect map. If a match occurs, it doesnot issue the command to the controller but instead substitute thealternative location as the new command.

[0082] Apart from the much higher speed of the solid-state disk, anotheradvantage is the lack of mechanical parts. The long seek times,rotational latency inherent in disk drives are not present. In addition,the long synchronization times, sync mark detects and write gaps are notrequired. Thus the overhead needed for accessing the location where datais to be read or written is much less. All of these simplifications andlack of constraints result in a much faster system with much reducedoverheads. In addition, the files can be arranged in memory in anyaddress order desired, only requiring the controller to know how to getat the data as needed.

[0083] Another feature of the invention is that defect mapping isimplemented without the need to interrupt the data stream transferred toor from the sector. The data in a block which may contain errors aretransferred regardless, and is corrected afterwards. Preserving thesequential addressing will result in higher speed by itself. Further, itallows the implementation of an efficient pipeline architecture in theread and write data paths.

[0084] Write Cache System

[0085] Cache memory is generally used to speed up the performance ofsystems having slower access devices. For example in a computer system,access of data from disk storage is slow and the speed would be greatlyimproved if the data could be obtained from the much faster RAM.Typically a part of system RAM is used as a cache for temporarilyholding the most recently accessed data from disk. The next time thedata is needed, it may be obtained from the fast cache instead of theslow disk. The scheme works well in situations where the same data isrepeatedly operated on. This is the case in most structures and programssince the computer tends to work within a small area of memory at a timein running a program. Another example of caching is the using of fasterSRAM cache to speed up access of data normally stored in cheaper butslower DRAM.

[0086] Most of the conventional cache designs are read caches forspeeding up reads from memory. In some cases, write caches are used forspeeding up writes to memory. However in the case of writes to systemmemory (e.g. disks), data is still being written to system memorydirectly every time they occur, while being written into cache at thesame time. This is done because of concern for loss of updated datafiles in case of power loss. If the write data is only stored in thecache memory (volatile) a loss of power will result in the new updatedfiles being lost from cache before having the old data updated in systemmemory (non-volatile). The system will then be operating on the old datawhen these files are used in further processing. The need to write tomain memory every time defeats the caching mechanism for writes. Readcaching does not have this concern since the data that could be lostfrom cache has a backup on disk.

[0087] In the present invention, a system of Flash EEprom is used toprovide non-volatile memory in place of traditional system memories suchas disk storage However, Flash EEprom memory is subject to wearing outby excessive program/erase cycles. Even with the improved Flash EEprommemory device as disclosed in copending U.S. patent applications, Ser.No. 204,175 and one entitled “Multi-state EEprom Read and Write Circuitsand Techniques,” by Sanjay Mehrotra and Dr. Eliyahou Harari filed on thesame day as the present application, the endurance limit isapproximately 10⁶ program/erase cycles. In a ten-year projected lifetime of the device, this translates to a limit of one program/erasecycle per 5 minutes. This may be marginal in normal computer usage.

[0088] To overcome this problem, a cache memory is used in a novel wayto insulate the Flash EEprom memory device from enduring too manyprogram/erase cycles. The primary function of the cache is to act onwrites to the Flash EEprom memory and not on reads of the Flash EEprommemory, unlike the case with traditional caches. Instead of writing tothe Flash EEprom memory every time the data is updated, the data may beoperated on several times in the cache before being committed to theFlash EEprom memory. This reduces the number of writes to the FlashEEprom memory. Also, by writing mostly into the faster cache memory andreducing the number of writes to the slower Flash EEprom, an additionalbenefit is the increase in system write throughput.

[0089] A relatively small size cache memory is quite effective toimplement the present invention. This helps to overcome the problem ofdata loss in the volatile cache memory during a power loss. In thatevent, it is relatively easy to have sufficient power reserve tomaintain the cache memory long enough and have the data dumped into anon-volatile memory such as a specially reserved space in the FlashEEprom memory. In the event of a power down or and power loss to thesystem, the write cache system may be isolated from the system and adedicated rechargeable power supply may be switch in only to power thecache system and the reserved space in the Flash EEprom memory.

[0090]FIG. 8 illustrates schematically a cache system 701 as part of thecontroller, according to the present invention. On one hand the cachesystem 701 is connected to the Flash EEprom memory array 33. On theother hand it is connected to the microprocessor system (not shown)through a host interface 703. The cache system 701 has two memories. Oneis a cache memory 705 for temporarily holding write data files. Theother is a tag memory 709 for storing relevant information about thedata files held in the cache memory 705 A memory timing/control circuit713 controls the writing of data files from the cache memory 705 to theFlash EEprom memory 33. The memory control circuit 713 is responsive tothe information stored in the tag memory as well as a power sensinginput 715 with is connected through the host interface 703 via a line717 to the power supply of the microprocessor system. A power loss inthe microprocessor system will be sensed by the memory control circuit713 which will then down load al the data files in the volatile cachememory 705 to the nonvolatile Flash EEprom memory 33.

[0091] In the present invention, the Flash EEprom memory array 33 isorganized into sectors (typically 512 byte size) such that all memorycells within each sector are erasable together. Thus each sector may beconsidered to store a data file and a write operation on the memoryarray acts on one or more such files.

[0092] During read of a new sector in the Flash EEprom memory 33, thedata file is read out and sent directly to the host through thecontroller. This file is not used to fill the cache memory 705 as isdone in the traditional cache systems.

[0093] After the host system has processed the data within a file andwishes to write it back to the Flash EEprom memory 33, it accesses thecache system 701 with a write cycle request. The controller thenintercepts this request and acts on the cycle.

[0094] In one embodiment of the invention, the data file is written tothe cache memory 705. At the same time, two other pieces of informationabout the data file are written to a tag memory 709. The first is a filepointer which identifies the file present in the cache memory 705. Thesecond is a time stamp that tells what time the file was last writteninto the cache memory. In this way, each time the host wishes to writeto the Flash EEprom memory 33, the data file is actually first stored inthe cache memory 705 along with pointers and time stamps in the tagmemory 709.

[0095] In another embodiment of the invention, when a write from thehost occurs, the controller first checks to see if that file alreadyexisted in the cache memory 705 or has been tagged in the tag memory709. If it has not been tagged, the file is written to the Flash memory33, while its identifier and time stamp are written to the tag memory709. If the file already is present in the cache memory or has beentagged, it is updated in the cache memory and not written to the Flashmemory. In this way only infrequently used data files are written intothe Flash memory while frequently used data files are trapped in thecache memory.

[0096] In yet another embodiment of the invention, when a write from thehost occurs, the controller first checks to see if that data file hasbeen last written anywhere within a predetermined period of time (forexample, 5 minutes). If it has not, the data file is written to theFlash memory 33, while its identifier and time stamp are written to thetag memory 709. If the data file has been last written within thepredetermined period of time, it is written into the cache memory 705and not written to the Flash memory. At the same time, its identifierand time stamp are written to the tag memory 709 as in the otherembodiments. In this way also, only infrequently used data files arewritten into the Flash memory while frequently used data files aretrapped in the cache memory.

[0097] In all embodiments, over time the cache memory 705 will start tofill up. When the controller has detected that some predetermined stateof fullness has been reached, it begins to archive preferentially somefiles over others in the cache memory 705 by writing them to the Flashmemory 33.

[0098] In either embodiments, over time the cache memory 705 will startto fill up. When the controller has detected that some predeterminedstate of fullness has been reached, it begins to archive preferentiallysome files over others in the cache memory 705 by writing them to theFlash memory 33. The file identifier tag bits for these files are thenreset, indicating that these files may be written over. This makes roomfor new data files entering the cache memory.

[0099] The controller is responsible for first moving the least activefiles back into the Flash memory 33 to make room for new active files.To keep track of each file's activity level, the time stamp for eachfile is incremented by the controller at every time step unless reset bya new activity of the file. The timing is provided by timers 711. Atevery time step (count), the controller systematically accesses eachdata file in the cache memory and reads the last time stamp written forthis data file. The controller then increments the time stamp by anothertime step (i.e. increments the count by one).

[0100] Two things can happen to a file's time stamp, depending on theactivity of the file. One possibility is for the time stamp to be resetin the event of a new activity occurring. The other possibility is thatno new activity occurs for the file and the time stamp continues toincrement until the file is removed from the cache. In practice amaximum limit may be reached if the time stamp is allowed to increaseindefinitely. For example, the system may allow the time stamp toincrement to a maximum period of inactivity of 5 minutes. Thus, when adata file is written in the cache memory, the time stamp for the file isset at its initial value. Then the time stamp will start to age,incrementing at every time step unless reset to its initial value againby another write update. After say, 5 minutes of inactivity, the timestamp has incremented to a maximum terminal count.

[0101] In one embodiment of keeping count, a bit can be shifted oneplace in a shift register each time a count increment for a file occurs.If the file is updated (a new activity has occurred) the bit's locationwill be reset to the initial location of the shift register. On theother hand, if the file remains inactive the bit will eventually beshifted to the terminal shift position. In another embodiment, a countvalue for each file is stored and incremented at each time step. Aftereach increment, the count value is compared to a master counter, thedifference being the time delay in question.

[0102] Thus, if a file is active its incremented time stamp is resetback to the initial value each time the data file is rewritten. In thismanner, files that are constantly updated will have low time stampidentifiers and will be kept in cache until their activity decreases.After a period of inactivity has expired, they acquire the maximum timestamp identifiers. The inactive files are eventually archived to theFlash memory freeing space in the cache memory for new, more activefiles. Space is also freed up in the tag memory when these inactivefiles are moved to the Flash memory.

[0103] At any time when room must be made available for new data filescoming into the cache memory, the controller removes some of the olderfiles and archives them to the Flash memory 33. Scheduling is done by amemory timing/control circuit 713 in the controller. The decision toarchive the file is based on several criteria. The controller looks atthe frequency of writes occurring in the system and looks at how fullthe cache is. If there is still room in the cache, no archiving need tobe done. If more room is needed, the files with the earliest time stampsare first removed and archived to the Flash memory.

[0104] Although the invention has been described with implementation inhardware in the controller, it is to be understood that otherimplementations are possible. For example, the cache system may belocated elsewhere in the system, or be implemented by software using theexisting microprocessor system. Such variations are within the scope ofprotection for the present invention.

[0105] The Profile of how often data is written back to the Flash memoryis determined by several factors. It depends on the size of the cachememory and the frequency of writes occurring in the system. With a smallcache memory system, only the highest frequency files will be cached.Less frequently accessed files will also be cached with increasing cachememory size. In the present invention, a relatively cheap and smallamount of cache memory, preferably about 1 Mbyte, may be used to goodadvantage. By not constantly writing the most active files (the top 5%),the write frequency of the Flash EEprom may be reduced from the usualone every millisecond to one every 5 minutes. In this way the wear-outtime for the memory can be extended almost indefinitely. Thisimprovement is also accompanied by increased system performance duringwrite.

[0106] Incorporating time tag into the write cache concept has theadvantage that the size of the write cache buffer memory can berelatively small, since it is used only to store frequently written datafiles, with all other files written directly into the Flash EEprommemory. A second advantage is that the management of moving data filesin and out of the write cache buffer can be automated since it does notrequire advanced knowledge of which data files are to be called next.

[0107] The various aspects of the present invention that have beendescribed co-operate in a system of Flash EEprom memory array to makethe Flash EEprom memory a viable alternative to conventionalnon-volatile mass storage devices.

[0108] While the embodiments of the various aspects of the presentinvention that have been described are the preferred implementation,those skilled in the art will understand that variations thereof mayalso be possible. Therefore, the invention is entitled to protectionwithin the full scope of the appended claims.

In the claims:
 1. A Flash EEprom system comprising: one or moreintegrated circuit chips each having an array of Flash EEprom cellspartitioned into a plurality of sectors, each sector addressable forerase such that all cells therein are erasable simultaneously; means forselecting a plurality of sectors among the one or more chips for eraseoperation; and means for simultaneously performing the erase operationon only the plurality of selected sectors.
 2. A Flash EEprom system asin claim 1, including read or write operations on chips which have beenenabled by a chip select signal, wherein the erase operation isperformed on chips without regard to the chip select signal.
 3. A FlashEEprom system as in claim 1, wherein the erase operation may beperformed on the plurality of sector selected for erase operation, whileread, write or other operations may be performed on any other device notselected for erase operation.
 4. The Flash EEprom system according toclaim 1, further comprising: means for individually removing any one orcombination of sectors from the plurality of selected sectors, such thatsaid removed sectors are prevented from further erase during the eraseoperation.
 5. The Flash EEprom system according to claim 1, furthercomprising: means for simultaneously deselecting all sectors.
 6. TheFlash EEprom system according to claim 1, wherein the selecting meansfurther comprises: individual register associated with each sector forholding a status to indicate whether the sector is selected or not. 7.The Flash EEprom system according to claim 6, wherein the simultaneouslyerasing means is responsive to the status in each of the individualregisters, such that only the selected sectors are included in theerasing.
 8. The Flash EEprom system according to claim 6, wherein anyone or combination of the individual registers indicating a selectedstatus are individually resettable to an un-selected status.
 9. TheFlash EEprom system according to claim 6, wherein all the individualregisters are simultaneously resettable to a status indicating theassociated sectors as not selected.
 10. A system for correcting errorsfrom defective cells within an array of Flash EEprom cells, comprising:substitute cells; means for substituting one or more of the defectivecells with a corresponding number of substitute cells.
 11. A system forcorrecting errors from defective cells within an array of Flash EEpromcells as in claim 10 wherein the substituting means also appliesautomatically to new defective cells as soon as they are detected.
 12. Asystem for correcting errors from defective cells within an array ofFlash EEprom cells as in claim 10, said array being partitioned into aplurality pf Flash erasable sectors such that all cells within eachsector are erasable at once, wherein the substitute cells are in thesame sector as the defective cells.
 13. A system for correcting errorsfrom defective cells within an array of Flash EEprom cells as in claim11, further comprising a defect map for storing defect pointers whichlink the addresses of the defective cells to that of the correspondingsubstitute cells.
 14. A system for correcting bad data in defectivecells within an array of Flash EEprom cells as in claim 13, wherein thedefect map for said defective cells are located in the same sector assaid defective cells.
 15. A system for correcting errors from defectivecells within an array of Flash EEprom cells as in claim 10, said arraybeing partitioned into a plurality of Flash erasable sectors such thatall cells within each sector are erasable at once, wherein thesubstitute cells are in the same sector as the defective cells when thenumber of defective cells in the sector does not exceed a predeterminednumber, and the substitute cells are in a different sector when thenumber is exceeded.
 16. A system for correcting errors from defectivecells within an array of Flash EEprom cells as in claim 15, wherein saidsector is replaced in its entirety by a substitute sector when saidnumber is exceeded.
 17. A system for correcting errors from defectivecells within an array of Flash EEprom cells as in claim 15 wherein thesubstituting means also applies automatically new defective cells assoon as they are detected.
 18. A system for correcting errors fromdefective cells within an array of Flash EEprom cells as in claim 17,including the use of error correction codes.
 19. A system for correctingbad data in defective cells within an array of Flash EEprom cells,comprising: substitute cells for storing good data intended for thedefective cells; means for substituting the bad data in one or more ofthe defective cells with the good data in the corresponding substitutecells when the defective cells are accessed.
 20. A system for correctingbad data in defective cells within an array of Flash EEprom cells as inclaim 19, further comprising means for automatically saving the gooddata intended to be written to the defective cells to the correspondingsubstitute cells, thereby preserving the integrity of the good data. 21.A system for correcting bad data in defective cells within an array ofFlash EEprom cells as in claim 20 wherein the substituting means alsoapplies automatically to new defective cells as soon as they aredetected.
 22. A system for correcting bad data in defective cells withinan array of Flash EEprom cells as in claim 20, said array beingpartitioned into a plurality of Flash erasable sectors such that allcells within each sector are erasable at once, and data is storedtherein, wherein the substituting means applies after the data includingthe bad data has been accessed.
 23. A system for correcting bad data indefective cells within an array of Flash EEprom cells as in claim 20,said array being partitioned into a plurality of Flash erasable sectorssuch that all cells within each sector are erasable at once, wherein thesubstitute cells are in the same sector as the defective cells.
 24. Asystem for correcting bad data in defective cells within an array ofFlash EEprom cells as in claim 20, further comprising a defect map forstoring defect pointers which link the addresses of the defective cellsto that of the corresponding substitute cells.
 25. A system forcorrecting bad data in defective cells within an array of Flash EEpromcells as in claim 24, wherein the defect map for said defective cellsare located in the same sector as said defective cells.
 26. A system forcorrecting bad data in defective cells within an array of Flash EEpromcells as in claim 19, said array being partitioned into a plurality ofFlash erasable sectors such that all cells within each sector areerasable at once, wherein the substitute cells are in the same sector asthe defective cells when the number of defective cells in the sectordoes not exceed a predetermined number, and the substitute cells are ina different sector when the number is exceeded.
 27. A system forcorrecting bad data in defective cells within an array of Flash EEpromcells as in claim 26, wherein said sector is replaced in its entirety bya substitute sector when said number is exceeded.
 28. A system forcorrecting bad data in defective cells within an array of Flash EEpromcells as in claim 26, wherein the substituting means also appliesautomatically to newly occurring defective cells
 29. A system forcorrecting bad data in defective cells within an array of Flash EEpromcells as in claim 28, including use of error correction codes.
 30. Animproved system for writing data files into a Flash EEprom memorycomprising: a cache memory for temporarily storing data files intendedfor the Flash EEprom memory, said cache memory able to undergosignificantly more write/erase cycles than the Flash EEprom memory;means responsive to a system write to the Flash EEprom memory forwriting data files into the cache memory instead of the Flash EEprommemory; means for identifying each data file in the cache memory; meansfor determining the time since each data file was last written; andmeans for first moving data file having the longest time since lastwritten from the cache memory to the Flash EEprom memory when additionalspace for new data files is required in the cache memory, therebysubstantially reducing the number of actual writes and associated stressto the Flash EEprom memory.
 31. The improved system as in claim 30,further comprising: a backup non-volatile memory for downloading thedata files in the cache memory thereto; and means responsive to animpending power loss for down loading the data files in the cache memoryto the backup memory, thereby saving the data files from the possiblyvolatile cache memory.
 32. The improved system as in claim 30, whereinthe backup memory is part of the Flash EEprom memory.
 33. The improvedsystem as in claim 30, wherein the cache memory has a significantlyfaster access time than that of the Flash EEprom memory.
 34. Theimproved system as in claim 30, including a controller circuit chip forcontrolling the operations of the Flash EEprom memory, wherein theimproved system is part of the controller circuit chip.
 35. The improvedsystem as in claim 30, including a microprocessor system and randomaccess memory, wherein the improved system is implemented by software inthe microprocessor system with random access memory.
 36. An improvedsystem for writing data files into a Flash EEprom memory comprising: acache memory for temporarily storing data files intended for the FlashEEprom memory, said cache memory able to undergo significantly morewrite/erase cycles than the Flash EEprom memory; means responsive to asystem write to the Flash EEprom memory for writing data files into thecache memory instead of the Flash EEprom memory; a tag memory forstoring the identity of data files and the time each data file was lastwritten; and means for first moving data file having the longest timesince last written from the cache memory to the Flash EEprom memory whenadditional space for new data files is required in the cache memory,thereby substantially reducing the number of actual writes andassociated stress to the Flash EEprom memory.
 37. The improved system asin claim 36, further comprising: a backup non-volatile memory fordownloading the data files in the cache memory thereto; and meansresponsive to an impending power loss for down loading the data files inthe cache memory to the backup memory, thereby saving the data filesfrom the possibly volatile cache memory.
 38. The improved system as inclaim 36, wherein the backup memory is part of the Flash EEprom memory.39. The improved system as in claim 36, wherein the cache memory has asignificantly faster access time than that of the Flash EEprom memory.40. The improved system as in claim 36, including a controller circuitchip for controlling the operations of the Flash EEprom memory, whereinthe improved system is part of the controller circuit chip.
 41. Theimproved system as in claim 36, including a microprocessor system andrandom access memory, wherein the improved system is implemented bysoftware in the microprocessor system with random access memory.
 42. Animproved system for writing data files into a Flash EEprom memorycomprising: a cache memory for temporarily storing data files intendedfor the Flash EEprom memory, said cache memory able to undergosignificantly more write/erase cycles than the Flash EEprom memory;means responsive to a system write to the Flash EEprom memory forwriting a data file either into the Flash EEprom memory or instead intothe cache memory, said responsive means writing to the Flash EEprom whenthe a previous copy of said data file is not present in the cachememory, and writing to the cache memory when a previous copy of saiddata file is present in the cache memory; and means for first movingdata files having the longest times since last written from the cachememory to the Flash EEprom memory when additional space for new datafiles is required in the cache memory, thereby substantially reducingthe number of actual writes and associated stress to the Flash EEprommemory.
 43. The improved system as in claim 42, further comprising: abackup non-volatile memory for downloading the data files in the cachememory thereto; and means responsive to an impending power loss for downloading the data files in the cache memory to the backup memory, therebysaving the data files from the possibly volatile cache memory.
 44. Theimproved system as in claim 42, wherein the backup memory is part of theFlash EEprom memory.
 45. The improved system for writing data files intoa Flash EEprom memory according to claim 42, wherein said responsivemeans for writing includes a tag memory for storing the identity of datafiles and the time each data file was last written, and wherein saidresponsive means writing to the Flash EEprom when said data file is nottagged in the tag memory, and writing to the cache memory when said datafile is tagged in the tag memory.
 46. An improved system for writingdata files into a Flash EEprom memory comprising: a cache memory fortemporarily storing data files intended for the Flash EEprom memory,said cache memory able to undergo significantly more write/erase cyclesthan the Flash EEprom memory; means responsive to a system write to theFlash EEprom memory for writing a data file either into the Flash EEprommemory or instead into the cache memory, said responsive means writingto the Flash EEprom when said data file is last written after thepredetermined period of time, and writing to the cache memory when saiddata file is last written within a predetermined period of time; andmeans for first moving data files having the longest times since lastwritten from the cache memory to the Flash EEprom memory when additionalspace for new data files is required in the cache memory, therebysubstantially reducing the number of actual writes and associated stressto the Flash EEprom memory.
 47. The improved system as in claim 46,wherein the cache memory has a significantly faster access time thanthat of the Flash EEprom memory.
 48. The improved system as in claim 46,including a controller circuit chip for controlling the operations ofthe Flash EEprom memory, wherein the improved system is part of thecontroller circuit chip.
 49. The improved system as in claim 46,including a microprocessor system and random access memory, wherein theimproved system is implemented by software in the microprocessor systemwith random access memory.
 50. An improved system for writing data filesinto a Flash EEprom memory comprising: a cache memory for temporarilystoring data files intended for the Flash EEprom memory, said cachememory able to undergo significantly more write/erase cycles than theFlash EEprom memory; a tag memory for storing the identity of data,files and the time each data file was last written; means responsive toa system write to the Flash EEprom memory for writing a data file eitherinto the Flash EEprom memory or instead into the cache memory, saidresponsive means writing to the Flash EEprom when the data file is notidentified in the tag memory, and writing to the cache memory when thedata file is identified in the tag memory; and means for moving firstthe data files having the longest times since last written from thecache memory to the Flash EEprom memory when additional space for newdata files is required in the cache memory, thereby substantiallyreducing the number of actual writes and associated stress to the FlashEEprom memory.
 51. The improved system as in claim 50, furthercomprising: a backup non-volatile memory for downloading the data filesin the cache memory thereto; and means responsive to an impending powerloss for down loading the data files in the cache memory to the backupmemory, thereby saving the data files from the possibly volatile cachememory.
 52. The improved system as in claim 50, wherein the backupmemory is part of the Flash EEprom memory.
 53. The improved system as inclaim 50, wherein the cache memory has a significantly faster accesstime than that of the Flash EEprom memory.
 54. The improved system as inclaim 50, including a controller circuit chip for controlling theoperations of the Flash EEprom memory, wherein the improved system ispart of the controller circuit chip.
 55. The improved system as in claim50, including a microprocessor system and random access memory, whereinthe improved system is implemented by software in the microprocessorsystem with random access memory.
 56. A memory card adapted to plug intoa computer system in a manner to communicate with a system bus and astandard power supply, comprising the following mounted thereon: aplurality of EEprom integrated circuit chips, each of said chipsincluding: a large number of individually addressable storage cellsorganized into a plurality of sectors, each sector containing aplurality of said storage cells, a plurality of spare storage cellswithin any of said sectors, means responsive to signals on said systembus for erasing all cells in one or more designated sectors withouterasing cells in others of said sectors, means responsive to signals onsaid system bus for reading the state of addressed storage cells, meansresponsive to signals on said system bus for programming addressedstorage cells to a predetermined state, and means responsive to anunsuccessful attempt to either program or erase a storage cell withinone of said sectors for substituting one of said spare storage cellstherefore while maintaining operation of the remaining cells of saidsector.
 57. The memory card according to claim 56 which additionallycomprises a cache memory mounted on said card, and wherein saidprogramming means includes means for initially programming said cachememory rather than said EEprom memory, said reading means includes meansfor initially determining whether the cache memory contains data to beread, and said programming means additionally includes means responsiveto said cache memory becoming full for writing its oldest unused blockof data into said EEprom memory, thereby to make room for new data insaid cache memory.
 58. The memory card as in claim 56, wherein each ofsaid chips further includes a plurality of spare sectors, and whereinsaid substituting means also substitutes one of said spare sectors forone of said sectors when a predetermined number of cells in said one ofsaid sector become defective.
 59. The memory card as in claim 58,including means for performing error correction using error correctioncodes.
 60. The memory card as in claim 56, including a controller and aninterface connected to the system bus, said controller being adapted tobe responsive to commands intended for a standard magnetic disk drivestorage system connectable to the computer system, thereby emulatingsaid disk drive system.
 61. The memory card as in claim 56, in whichvarious operating voltages are required for various operations of theEEprom chips, including means for generating the various operatingvoltages from the standard power supply.
 62. A storage systemincorporating therein the memory card of claim 56, comprising: acontroller for controlling the operation of the EEprom chips; means forgenerating voltages for the operation of the EEprom chips; means forerror correction in the operation of the storage system; and means forinterfacing the storage system to a computer system.